1. Field of the Invention
This invention relates generally to computer systems, and more particularly to the reduction of option ROM code stored in system RAM after boot-up of a computer system.
2. Description of the Related Art
Today""s personal computer systems provide users with a high degree of flexibility in terms of the number of peripheral devices that may be connected to a given system. For instance, users are able to connect additional internal and external peripheral devices to meet the storage or data access demands required to complete the user""s job. By way of example, users are able to connect additional internal or external hard drives, compact disc (CD) players, digital video disc (DVD) players, compact disc recordables (CD-Rs), etc.
To meet the connection needs for these peripheral devices, most computers have IDE connectors and PCI connectors built into the computer""s motherboard. Typically, the IDE connectors are used to connect internal devices, such as, hard drives and CD-ROM drives. The PCI connectors are generally configured to receive host adapter cards, which allow the connection of both internal and external devices. As is well known, there are numerous types of host adapters, some of the most commonly used are SCSI host adapters, redundant array of inexpensive disk (RAID) host adapters, and the like. SCSI host adapters are one of the most popular adapters due to peripheral device arrangement flexibility and performance. For instance, one SCSI host adapter can serve as the communication link for up to 15 internal and external peripheral devices.
Most host adapters have option ROM chips integrated onto the printed circuit board of the host adapter card. The option ROM chip is typically an electrically erasable programmable read only memory (EEPROM), which stores program instructions that are used during the boot process of the computer system that has the host adapter card connected thereto. Without these program instructions, the host adapter card and any of the peripheral devices connected to the host adapter card will not be able to communicate with the host computer system during the boot up time, and thus, the system may not be able to boot. Host adapters without a EEPROM can only be used as a secondary host adapter.
In server applications, there is typically an increased need for additional storage devices, such as, hard drives, tape drives, removable drives, and the like. To meet this demand, motherboard manufacturers typically integrate controller chips directly to the motherboard to decrease the need for additional host adapters. FIG. 1A shows a computer system 100 having a motherboard 102. The motherboard 102 has, in this example, two controller chips 108a and 108b. If the controller chips are SCSI controllers, they can provide communication for internal devices by way of a PCI bus 110. In this simplified example, the motherboard 102 is shown having a system RAM chip 104, and the PCI bus 110 connected to host adapters (HA) 106. Typically, the HAs 106 are connected to the motherboard 102 by way of the aforementioned PCI connectors that are integrated to the motherboard itself. Each of the HAs 106 generally have their own controller chips 108 and option ROM chips (not shown). The HAs 106 therefore, enable communication with external devices, such as, devices D1-D6. The controller chips 108 are configured to provide communication for devices D7 and D8. In order to reduce system cost, some server motherboard manufacturers integrate substantially more controller chips 108 directly to the motherboard, thus reducing the need for more expensive HA 106 cards.
Although in theory any number of controller chips can be integrated to the motherboard 102 and any number of HAs 106 can be connected to PCI slots, there is a limitation in that the system BIOS only allocates a certain fixed amount of memory space in system RAM chip 104 for the BIOS code utilized by each of the controller chips 108.
During boot up, the system BIOS, via the PCI bus, will locate each of the controller chips 108 connected to the computer system 100 and copy their associated option ROM BIOS into the system RAM 104 chip. As shown in FIG. 1B, the system RAM 104xe2x80x2 has a fixed amount of space that is allocated for all of the option ROM BIOS code. Typically, the range of allocated space ranges between address C000h and DFFFh (i.e., about 128 k of memory space).
When the option ROM code for a particular controller chip 108 is copied to the allocated system RAM 104xe2x80x2, the initialization code that is part of the option ROM code is also copied to the RAM 104xe2x80x2. Once the initialization code completes the initialization process for a particular controller chip (i.e., has identified each of the devices connected to the controller chip), the initialization code for that particular chip is removed from the RAM 104xe2x80x2. Accordingly, FIG. 1B assumes there was enough space in RAM 104xe2x80x2 for both the option ROM code (that includes runtime code (RTC) and initialization code) for each of the controller chips 108a-108d. However, when the RTC 113a and initialization code 113b for chip 108e is to be loaded to the RAM 104xe2x80x2, there may not be enough space remaining for the initialization code between address C000h and DFFFh. If this happens, the option ROM code for the controller chip 108e will not be copied to the RAM 104xe2x80x2, and therefore, the devices D4, D5, and D6 will not be made available to the users of the computer system 100.
Although in this simplistic example the runtime code (RTC) of the controller chips 108a-108d are successfully stored in the RAM 104xe2x80x2, many server manufacturers are using motherboards that have increasingly more controller chips 108. In view of the allocated memory space limitations in the system RAM 104xe2x80x2, the addition of more controller chips is resulting in situations where some devices are simply not available to users of the computer system.
In view of the foregoing, there is a need for an increased number of controller chips on motherboards, while reducing the usage of memory space in the option ROM code allocated memory space of a computer""s system RAM.
Broadly speaking, the present invention fills these needs by providing a computer implemented method for generating a single image BIOS that can be used with a selected number of controller chips, and for an option ROM BIOS having a generic option ROM and a table that facilitates the generation on only one image BIOS. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, computer readable media, or a device. Several inventive embodiments of the present invention are described below.
In one embodiment, a method for initializing controller chips of a computer system is disclosed. The method includes the operations of integrating a set of controller chips to a motherboard, and generating a table that identifies the set of controller chips and PCI device function addresses of the set of controller chips. The method then includes identifying one of the set of controller chips to be a master controlling chip and those other than the master controlling chip to be non-controlling chips. Then a single generic option ROM code is generated for the set of controller chips. Once generated, the table and the generic option ROM code is stored in a system BIOS ROM of the computer system during boot-up.
In another embodiment, a method for generating a single image BIOS that functions with a plurality of controller chips is defined. The method includes: (a) providing a motherboard with the plurality of controller chips; (b) generating a generic option ROM code that is configured to operate with each of the plurality of controller chips; (c) generating a table that identifies each of the plurality of controller chips, and a PCI device function address for each of the plurality of controller chips; the table further includes information as to which one of the plurality of controller chips is a master controlling chip and which are non-controlling chips, and the generating of the generic option ROM code and the table defines an option ROM code; (d) and storing the option ROM code to a system BIOS ROM that is part of the motherboard. In this embodiment, when the computer is booted up, only the generic option ROM code is loaded into the system RAM when the master controller chip is initialized, and the same generic option ROM code is configured to initialize all the remaining controller chips in the table.
In still a further embodiment, a motherboard having a system RAM chip, a set of controller chips, and a system BIOS ROM chip is disclosed. The system BIOS chip includes generic option ROM code and a table identifying each of the controller chips and associated PCI device function addresses for the controller chips. A selected one of the set of controller chips is defined as a master controlling chip, and it will communicate with the generic option ROM code for initialization each one of the set of controller chips.
Advantageously, one BIOS image can now control a set of controller chips that may be integrated as part of a computer system""s motherboard. Not only is less system RAM space used, but the system can now run faster because the controller chips already controlled by the one BIOS image will be skipped. In general, when a controller chip designated to be the master controlling chip gains control, the system is requested to list all of the devices plugged into the system. A check is then made as to which ones in the list can be controlled by the one BIOS image. The ones that can be controlled by the one BIOS will then be selected and generated into a table in the system memory (i.e., system option ROM chip). When the BIOS for a device gains control, a check is made to determine whether that selected device is identified in the table. If the selected device is in the table, the BIOS for that selected device will withdraw itself without loading a BIOS image into the system RAM. Accordingly, for all of the chips identified in the list, only one BIOS image will be copied into the system RAM. Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.